A low-power analog front end of passive UHF RFID tag IC for EPC™ C1G2

This work
¹
presents the design of a low-power analog front-end circuitry for fully integrated passive radio frequency identification tag operating at UHF for EPC
^TM
C1G2. The whole circuit includes voltage multiplier, voltage reference, voltage regulator, ASK demodulator, ring oscillator, power-on-reset and modulator. In this paper, ASK demodulator with digital control is proposed and a clock calibration method for ring oscillator is chosen. The entire circuit has been designed with SMIC 0.18 μm CMOS technology. Simulation results by cadence software show the analog front-end circuitry consumes less than 2.5 uW.