True low-voltage flash memory operations

This paper proposes true low-voltage operations for high-performance flash memory. The program and erase operations only need voltages not exceeding the junction breakdown voltage of CMOS technology. In this way, flash memory is easily integrated with CMOS logic circuits, since there is no special fabrication process for high-voltage junctions, gate oxide, and field isolation. Low-voltage programming is based on hot electron injection with Vcc on drain and gate. Low-voltage erase is based on Fowler-Nordheim (F-N) tunneling with negative gate bias and Vcc on source and careful grounding the n-well for negative voltage circuits. Low-voltage read operation is seriously degraded using conventional one-transistor (1T) cell due to reduced read current by low gate bias and not allowing operation in depletion. A 2-transistor (2T) cell structure is proposed for high speed read at low Vcc by allowing cell operation in depletion, precharging the cell gate, and switching the select transistor by Vcc. This scheme greatly simplifies the cost of integrating flash memory with logic circuits and is promising for future high-performance systems with low-voltage and low-power applications.