A high-performance low-power H.264/AVC video decoder accelerator for embedded systems

We present a high-performance and low-power pure-hardware accelerator for decoding H.264/AVC video. We propose novel VLSI architectures for every stage of the decoding pipeline. We wrap the decoder core with an AMBA bus interface, integrate it into a multimedia SOC platform, and verify it with FPGA prototyping. In order to reduce external memory traffic, we propose a memory fetch unit to increase the length of burst access. Running at a 16 MHz, our FPGA decoder prototype can real-time decode D1 video (720×480) at 30 fps. We also propose several techniques to reduce both average and peak power consumption. Simulation result shows that our design consumes only 21.2 mW of average power. The proposed H.264/AVC video decoder is suitable for embedded multimedia systems for mobile applications.