Low power discontinous-time comparator

This paper presents the design of a low power discontinuous time comparator. The designed comparator can be used in any circuit to decrease power consumption in stand-by mode. The design is based on a simple and efficient idea: while the comparator is in shut-down mode, its previous state is stored in a latch. This idea can be easily applied to any ldquoalready designedrdquo discontinuous - time comparator.