Managing annealing pattern effects in 45nm low power CMOS technology

We present a study of the pattern effects induced by spike and laser anneals in LP 45nm CMOS platform. A complete optical and thermal simulation methodology that provides the intra-field temperature mapping has been developed and validated by electrical measurement. This work enables significant improvements, by decreasing the optical dispersion, through an optimized dummification at long and short scale, possibly the use of an absorbent layer, and by reducing the temperature device sensitivity.