Impact of Epi-Si growth temperature on Ge-pFET performance

In this study, we report a direct comparison between two epitaxial silicon processes: 500degC using SiH
₄
and 350degC using Si
₃
H
₈
. Following four different metrics, we demonstrate that the reduction of silicon growth temperature results into the introduction of negatively charged defects possibly located at the Si/SiO
₂
interface. However, the Epi Si growth at 350degC with Si
₃
H
₈
remains beneficial compared to a growth performed at 500degC-SiH
₄
especially when thin EOT Ge pFETs are targeted.