An 8th-order MASH delta-sigma with an OSR of 3

This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1
^st
-order stages with an oversampling ratio of 3 and realized in a 0.18 mum CMOS process. The modulator attains an SNDR of 60 dB at a 50 MHz sampling frequency and an 8.33 MHz input bandwidth.