Clock data recovery based on delay chain for medium data rate transmission

Most mature clock and data recovery (CDR) circuits are used for high data rate (gigabit), few of them can be used in medium date rate. A digital CDR method based FPGA is raised to archive medium and low data rate serial digital communication, which can use simple line transceivers. The CDR circuit consist an FPGA, a VCO, and a loop filter. The FPGA implement the Phase detector. In the FPGA, a delay chain is constructed by a serial of delay chain taps. Each tap produces same amount of delayed time. The input signal is sent through the delay chain. Every output of the delay chain taps are sampled by the VCO output clock. The sampled result is compared to find the transition of data. Then the phase difference between the input signal and the VCO output clock can be obtained. The VCO control voltage is adjust to reduce the phase difference and archive phase lock. A second-order passive loop filter is used to filter the output of the phase detector. To make the loop work fine, the values of the resistances and capacitances of the loop filter are calculated from the parameters of the delay chain and the VCO, getting proper damping factor and natural frequency of the loop. Finally, an experiment based on XILINX spartan3E FPGA was made to build a 64Mbps transmission. The results show that the clock of the transmission was correctly recovered while the jitter was less than 2ns.