OASYS: A Framework for Analog Circuit Synthesis

A hierarchically structured framework for analog circuit synthesis is described. Analog circuit topologies are represented as a hierarchy of templates of abstract functional blocks (called design styles) each with associated detailed design knowledge. This hierarchical structure has two important features: it decomposes the design task into a sequence of smaller tasks with uniform structure, and it simplifies the reuse of design knowledge. Mechanisms are described to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower, more concrete level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers from performance specifications and process parameters. Measurements from detailed circuit simulation, and from actual fabricated analog IC's based on OASYS-synthesized designs demonstrate that OASYS is capable of synthesizing functional circuits.