Miniature wireless activity monitor using 3D system integration

Unobtrusive and continuous measurement of body parameters such as activity, movement, heartbeat, temperature and oxygen level in blood offers many opportunities in the health and fitness area: distant patient monitoring, rehabilitation support, activity stimulation, improved training programs in sports and even sleep management become possible. Enablers are small wireless body sensors that send the data to a computer or communication device. A key factor in many such applications is unobtrusiveness to the user. This requires miniaturization and, consequently, a high level of integration. Contrary to planar integration, 3D Si-level integration allows reduction of area and combination of different technologies. In the European project e-CUBES, a wireless activity monitor has been developed to demonstrate such a device can be realized by stacking integrated passives, embedded thinned IC's and SMDs. Besides the power management section, which is on the stacked PCB, the circuit is vertically integrated on a Si substrate in four layers: 1. integrated passives made by means of thin film dielectric and metallization processes, 2. embedded thinned (down to 20 mum) active dies and vertical interconnects, 3. re-distribution layer, and 4. SMD and flip-chip components. New in this concept are: combination of integrated passives and embedded active dies, an SMD component on top of an embedded micro processor die, and a one-chip embedded 17 GHz transmitter with a one-chip RF resonator. The antenna is mounted on the silicon backside and is fed by a slot coupling structure in the silicon to eliminate a wired connection to the antenna. Wireless battery charging and wireless on/off switching make it possible to put the system in a sealed package. By using 3D system integration, especially in applications containing RF functions, very low interconnect parasitics are achievable (as compared to wire bonding and even flip chip mounting). A successful demonstrator opens the way for thinning more dies and stacking more layers without using through silicon vias, so standard bare wafers can be used without design changes.