A design approach to increase gain feature of a Doherty Power Amplifier

One of the main drawback of the Doherty architecture is related to the intrinsic lower power gain attainable with respect to the nominal value assured by the Main amplifier. A proposed solution, discussed in this paper, is based on the use of different bias voltages for the Main and Auxiliary amplifiers. To validate the methodology, a Doherty Power Amplifier (DPA) in LDMOS technology is presented. The DPA is designed to operate at 2.14 GHz (UMTS), based on two equal devices with 17.4 mm of gate periphery. An uneven power splitter based on Branch Line coupler is adopted to deliver more power to the Auxiliary device. A saturated output power (Pout) of 43 dBm with a drain (power added) efficiency of 47% (43.5%) have been measured, with a corresponding power gain of 11 dB. The drain (power added) efficiency is kept higher than 36% (33%) in a 6 dB of Output back-off (OBO) with an almost constant behaviour.