A low complexity VLSI architecture for MIMO sphere decoding algorithm

This paper presents a low complexity VLSI architecture for depth-first sphere decoding algorithm. A modified depth first sphere decoding algorithm that requires less hardware resources and provides higher throughput has been introduced. In order to implement the proposed algorithm, we introduce a new enumeration methodology that can be used for M-QAM based modulation schemes. The effectiveness of the proposed architecture has been demonstrated for a 4times4 64-QAM MIMO system.