Risk management of LSI design by spice parameter QA methodology

Determination of Spice model parameter requires significant technology challenges for successful LSI design. Especially, MOSFET model parameters, such as ones used in BSIM, PSP and HiSIM, have to guarantee the physical consistency, experimental accuracy, smoothness of conductance and computational efficiency. To verify these requirements on the Spice parameters, various QA methodology and tools have been proposed and evaluated their ability. However, very few works have been done to conduct such parameter QA works systematically, so far. To address this issue, we have developed the spice parameter QA methodology, and practice it using for plural parameters through spice parameter extraction contest. In this paper, we will show an interesting experiment by spice parameter extraction contest. Six challengers accepted this contest work and provided their original parameters for BSIM4.5. They are actually different parameters, depending on the engineer's carrier and so-on. We have evaluated each of the parameter quality based on our proposed methodology. By ranking the quality fairly and comprehensively, we have analyzed the weakness and strength of the extracted parameter sets. Details of the parameter QA results will be discussed. On the other hand, we suggest that its quantitative results have a potential ability to decrease excessive margin avoiding risk of LSI design.