A 1.5mW 16b ADC with improved segmentation and centroiding algorithms and litho-friendly physical design (LFD) used in space telescope imaging applications

This paper describes a 1.5 mW cryogenically-cooled 16 b ADC x36-array in a 250 nM CMOS ASIC. The ADC uses a combination of improved MSB-LSB segmentation, 3 centroiding algorithms and litho-friendly physical design (LFD) to achieve < 0.4 b DNL and < 2.3 b INL at 100 KSPS without requiring initial or background calibration.