A heterogeneous digital signal processor implementation for dynamically reconfigurable computing

This paper describes a system on chip (SoC) implementation of a heterogeneous multi-core digital signal processor, that exploits different flavours of reconfigurable computing, merged together in a highly-parallel on chip interconnect utilized for data, configuration and control. The device incorporates an embedded field programmable gate array (eFPGA), a mid-grain intensive-computation reconfigurable datapath (DREAM), and a coarse grain reconfigurable array (PACT XPP) integrated on 3 independent clock islands. On a fourth global clock island an ARM processor manages communication, configuration and synchronization between the cores. The device joins the flexibility of the three heterogeneous run-time configurable engines together with the dynamic frequency scaling techniques enabling performance/power tuning. The SoC was implemented in 90 nm CMOS technology and is 110 mm
²
. It performs several GOP/S, depending on operation granularity.