Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors

The phenomena and mechanisms of hot-carrier-induced threshold-voltage (
V

_T
) shift in high-voltage p-type laterally diffused MOS (LDMOS) transistors are investigated. At low-|
V

_gs
| (absolute value of gate voltage) stress condition, electrons are injected and trapped in the gate oxide at the channel region near the drain, resulting in
V

_T
increase (Delta|V
_T
| < 0). At high-|
V

_gs
| stress condition, however, severe
V

_T
decrease (Delta|V
_T
| > 0) is found after stress. Experimental results suggest that donor-type interface traps created by hole injection in the channel region is the dominant factor for
V

_T
decrease.