Rapid and Accurate Timing Modeling for SRAM Compiler

Static random access memory is usually used in the ASIC design. The performances of memory always play major role in the overall circuit. In this paper, we propose an efficient extrapolation-based timing modeling method for SRAM complier. We build the timing equation of access and cycle time of SRAM. Our proposed method only needs to simulate a small number of memory configurations with relatively small sizes. The obtained results are extrapolated to any other configurations. In order to obtain the SRAM macros, we develop the SRAM compiler. Our proposed method is approximately 5% average error.