A passive RFID tag IC development platform

This paper presents a development platform to generate passive UHF RFID tags compatible with EPC
^TM
C1G2 protocol. The platform is based on one RFID tag IC prototype implemented in a 130nm CMOS technology. Some features of the tag IC include that a voltage multiplier implemented by diode-connected NMOSFETs, a voltage regulator composed of a self-biased mutual compensation without large resistors for area-saving, and an energy-aware irregular clock structure with clock gating used in the baseband processor. To further reduce the chip area for low production cost and meet different specifications, the platform design manages to achieve different floorplans according to different user-defined requirements, mainly focusing on the communicating distances. This approach simplifies the design flow, and, most importantly, shortens time-to-market.