Design of a VLSI fuzzy processor for ATM traffic sources management

Traffic management in ATM networks aims for the controlled use of network resources to prevent the network from becoming a bottleneck. This is a very complex task due to the random nature of the traffic arrival pattern and contention for network resources. In this paper we deal with one of the most important aspects of traffic control: "the policing". It has the role of ensuring that each source complies with the traffic parameter negotiated, in order to avoid network congestion. We present a policing mechanism based on Fuzzy Logic. As far as selectivity and dynamic response are concerned, it outperforms traditional mechanism thanks to the softness which characterizes Fuzzy Logic. In the paper we also address the design of a VLSI fuzzy processor to implement the mechanism in hardware. The processor is organized as a cascade of pipeline stages in which fuzzy inferences are processed in parallel. A synthesis on CMOS 0.5 /spl mu/m technology has allowed the processor to reach a very high processing speed occupying only a few mm/sup 2/ of silicon area, thus requiring a very low implementation cost.