Clock duplicity for high-precision timestamping in Gigabit Ethernet

Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual muP-based implementations fail on deterministic timestamp retrieval and insertion inside the message. This problem degrades significantly the synchronization between network nodes. This paper describes the analysis, implementation, and evaluation of a HW-timestamping technique for minimal-latency timestamping at Gigabit Ethernet using a low-cost off-the-shelf FPGA board. The effectiveness of the method is validated through a point-to-point synchronization scheme achieving a best-case synchronization accuracy of 150 ns.