Advances in CMOS Circuits

This chapter contains sections titled:

• Deep-Submicron CMOS Warms up to High-Speed Logic

• High-Speed Compact Circuits with CMOS

• Design-Performance Trade-Offs in CMOS-Domino Logic

• NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures

• Cascode Voltage Switch Logic: A Differential CMOS Logic Family

• Differential Split-Level CMOS Logic for Subnanosecond Speeds

• A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic

• Pass-transistor Networks Optimize n-MOS logic

• A 3.8-ns CMOS 16 �� 16-b Multiplier Using Complementary Pass-Transistor Logic

• Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs

• A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic

• A 4.4-ns CMOS 54��54-b Multiplier Using Pass-Transistor Multiplexer

• Pass-Transistor Dual Value Logic for Low-Power CMOS

• Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems

• A High Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications

• 0.5V SOI CMOS Pass-Gate Logic