Lithography technology development and design rule consideration for 0.4-0.35 /spl mu/m DRAM semiconductor processes

The practical issues of i-line lithography process development and design rule considerations for 0.4-0.35 /spl mu/m DRAM (dynamic random access memory) manufacturing were addressed in this paper. Based on published literature and our development experience in 64 Mb DRAM, a list of lithography requirements for DRAM manufacturing was proposed and discussed. The details on focus budget issue were discussed also. A tremendous DOF (depth of focus) loss on the critical layer processes occurred without the considerations of local and global proximity effects and metrology errors on 0.4 /spl mu/m and below processes. Combining an optical proximity correction (OPC) technique with design rule modifications, a factor of 2-3 improvement in UDOF (usable DOF) was proven. Thinner resist thickness and mask quality control which become inevitable for the coming generations were discussed also.