Minimizing power dissipation in non-zero skew-based clock distribution networks

A methodology is presented in this paper for synthesizing low power clock distribution networks. The clock distribution networks are designed with localized non-zero clock skew so as to improve circuit performance and reliability. Each branch of the clock tree is assigned a delay value that is emulated by one or more CMOS inverters, each designed such that the output load appears as being predominantly capacitive. A design technique is presented for selecting the size and number of inverters within each branch such that the total power dissipated within the clock distribution network is minimized. The power dissipation model considers both dynamic and short circuit power components. Simulation results exhibit reductions of up to 25% in total power dissipation within the clock distribution network, while accurately implementing the desired clock skews.