Design methodology for low power data compressors based on a window detector in a 54/spl times/54 bit multiplier

Currently, a typical 54/spl times/54 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is a design methodology for the low power data compressors based on an intelligent window detector. The role of the window detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a window) is activated. Therefore, it can be called an intelligent window detector. Using it, the average power consumption of the proposed data compressors is reduced by about 35%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one.