Post-CTS clock skew scheduling with limited delay buffering

Proposed post-clock-tree-synthesis (CTS) optimization method is delay buffering at the leaves of the clock tree to implement a limited version of clock skew scheduling. The method suggests the limitation of delay buffering on each clock tree branch as well as a global monitoring of total amount of delay buffering to improve the circuit performance. The delay buffering for non-zero clock skew operation is performed only after the clock sinks in order to preserve the structure and the optimizations implemented with any clock tree synthesis methodology. Experimental results demonstrate the superiority of the proposed post-CTS methodology over previous methods and demonstrate an important trend of clock period improvement over varying upper bounds of delay buffering. It is shown that the majority of the clock period improvement achievable through clock skew scheduling is obtained through very limited buffering (ap43% average improvement through 10% of max buffering).