An approximation method for modeling a CMOS bit-level product cell

An approximation method for a CMOS bit-level product cell used for vector-matrix multiplications is presented. The quantitative mathematical model of the cell is obtained by using CID/CCD principles to understand the device function and employing MOS structure equations to describe the cell operation. Due to the resultant equation cannot be solved explicitly, a multilayer artificial neural network is proposed to do functions approximations. The resultant algorithm is used to create an electrical device model for PSPICE simulations.