Gate leakage in Low Standby Power 16 nm gate length Double-gate MOSFETs

Leakage power, due to the tunneling gate current, increases aggressively with the scaling of the insulator thickness. Low Standby Power (LSTP) devices are typically designed for low power applications that put strict limits on the gate current. In this work a widely used model for the tunneling gate current in bulk MOSFET is modified to suit the Double-gate (DG) MOSFET. The modification is made to include quantum mechanical effects. Then, the model is used to study the gate leakage in a 16 nm gate length DG MOSFET LSTP transistor that is projected by the International Technology Roadmap for Semiconductors (ITRS) to be fabricated in the year 2015. In this study, the gate current is calculated for different candidates of dielectric materials. Specifically, nine dielectric materials were used. The simulated gate current is found to be 5.36×10
³
A/cm
²
when SiO
2
was used as a dielectric and 338.76 A/cm
²
when Si
3
N
4
was used. These two values exceed the maximum allowed gate current density (J
g,limit
) projected by ITRS for this device which is 0.188 A/cm
²
. The lowest obtained gate current density was 2.66×10
⁻¹¹
A/cm
²
when La
2
O
3
was used.