Double patterning lithography friendly detailed routing with redundant via consideration

In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achieve high quality solution for DPL-unfriendly designs, due to complex 2D patterns in lower metal layers. Therefore, DPL-friendliness is needed at routing stage [3]. Another key yield improvement technique is redundant via insertion [4] [5]. However, this would increase the complexity in DPL-compliance. To make designs manufacturable in DPL, we should not insert a redundant via if it results in coloring conflict. This paper is the first work to consider DPL and redundant via together. We have developed two algorithms, post-routing DPL-aware insertion and DPL-friendly routing with redundant via consideration to take into account redundant via DPL-compliance. Experimental results show that, compared to a DPL-aware optimization flow without redundant via consideration, we can improve insertion rate by 43% while still achieving zero coloring conflicts. Moreover, we can reduce the number of vias and stitches by 9% and 17% respectively.