Architecture level design space exploration of superscalar processor for multimedia applications

In this paper, a variant of simulated annealing optimization has been used to derive a power efficient general purpose superscalar processor based on ARM Instruction Set Architecture. SimpleScalar architecture toolset in tandem with power estimation extension Wattch has been used for design space exploration. The use of common open source tools and models makes it easy to adapt the technique for other applications and architectures. MPEG2 decoder of the MPEG Software Simulation Group along with MP3 and JPEG decoders of MiBench Benchmark suite have been used to guide the architecture exploration. The optimization achieves an improvement in power of up to 50% for MPEG and JPEG decoders. The low transistor count and the ability of the optimum configuration to support complex real time multimedia standards makes it suitable for emerging handheld devices.