Efficient Computer-Aided Failure Analysis of Integrated Circuits using Scanning Electron Microscopy

A working, operational system for computer-aided failure analysis of integrated circuits using a scanning electron microscope (SEM) is described. Statistical data analysis and image-processing algorithms are applied to digitized SEM image data. Faults are automatically identified and characterized at the single transistor level. Data-storage requirements for locating and characterizing semiconductor device failures are evaluated. A working, operational method is presented which minimizes these requirements, increases throughput, and permits a high degree of automation.