Economics and design challenges in implementing CMOS Transimpedance Amplifers for 10Gb/s operation

This paper examines the technological challenges in implementing 10 Gb/s Transimpedance Amplifiers in standard CMOS process technology. Circuit techniques for enabling 10 Gb/s CMOS circuit operation are discussed. Paper concludes with measurements results for an actual 10 Gb/s CMOS Transimpedance Amplifier.