Failure Analysis of Memory Organization for Utilization in a Self-Repair Memory System

Traditional approaches to memory reliability have been limited to complete redundancy or coding techniques. Redundancy frequently proves too expensive (introducing additional systems faults) and the traditional memory coding techniques have been limited to those areas of memory where a single fault results in a single failure (e.g., a broken core in a magnetic memory) as distinguished from an address decoder fault. To take an integrated approach to this problem, using a variety of coding and modularization techniques on each of the memory subsystems, it is necessary to determine the types of faults and failures caused by these faults that could occur in the system. This paper presents the results of a failure analysis study of typical 2D, 2½D, and 3D memory organizations. Two-way memories are also considered. This study demonstrates that a 2D memory, utilizing a switching array for memory access, is less susceptible to eatastrophic failures than other organizations considered. A memory organization capable of distributing the failures, in a manner permitting correction by linear codes, was adopted. Other techniques for automatic replacement of fault units are also considered.