On the VLSI implementation of the international data encryption algorithm IDEA

This paper describes a new VLSI realization of the International Data Encryption Algorithm IDEA. The presented VLSI architecture is compared with the VINCI chip, the first silicon realization of the IDEA. Principal design aspects are also discussed. Although the VINCI circuit can be used for real-time encryption in high-speed networks such as ATM, there are requirements for VLSI circuits with faster encryption ability. Further, the implemented test during the normal operation in the VINCI chip cannot detect all possible errors. The proposed new implementation is motivated by the requirement for higher data rates and a new solution for the on-line test problem, which is a main task in implementing cryptographic algorithms. First design results show that the resulting circuit can achieve an encryption rate of about 355 Mb/s. This is achieved by the implementation of one round in a 0.8 /spl mu/m CMOS technology. The architecture includes a concurrent self-test based on a mod-3 residue code self-checking system which allows the detection of permanent and temporary single- and multiple-bit errors in the IDEA datapath and hence the secure prevention of faulty encrypted or decrypted data.