Mutual exploration of FinFET technology and circuit design options for implementing compact brute-force latches

Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-V
_th
) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay, setup time, leakage power consumption, layout area, and static noise margin. The clock power is minimized with the multi-V
_th
latches that combine the independent-gate bias and gate underlap engineering techniques. Alternatively, the total active mode power and the leakage power are minimized with the multi-V
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latches that combine the independent-gate bias and work-function engineering techniques. With the multi-V
_th
latches, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 50.3%, 22%, and 47%, respectively, while maintaining similar speed and data stability as compared to the standard single-V
_th
circuits. Furthermore, the area is reduced by up to 21% with the multi-V
_th
latches as compared to the circuits with single-V
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tied-gate transistors in a 32nm FinFET technology. The FinFET latches with gate-drain/source overlap engineering are easier to implement with fewer processing steps as compared to the previously published latches based on independent-gate bias and work-function engineering.