A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications

A differential data aware power supplied (D
²
AP) 8T-SRAM cell has been proposed to address the stability trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, this 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to enlarge both stability margins for write and half-select accesses. A boosted bitline scheme also improves read cell current. Two 45nm 39Kb SRAM macros, D
²
AP (this work) and conventional 8T were fabricated on the same testchip. The measured VDDmin for D
²
AP-8T is 240mV lower than that of the conventional 8T.