Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface

A 7Gb/s 1Gb GDDR5 DRAM is implemented in a 54nm DRAM process. In order to improve data valid window at high speed interface, it employs a duty-cycle corrector (DCC) which achieves wide-range and fast-lock time by utilizing an anti-harmonic asynchronous binary search (ABS) circuit, as well as optimizes capability of duty-cycle correction by using offset-tolerant duty-cycle detection scheme. The acceptable range of the DCC is ±100ps and the corrected duty-cycle is 50% ± 6ps. The DCC operates over a wide frequency range from 0.8GHz to 3.5GHz and consumes 4.5mW at 3.5GHz using a 1.5V supply voltage.