A dual-channel 10b 80MS/s pipeline ADC with 0.16mm2 area in 65nm CMOS

A dual-channel 10b 80MS/s low-power and area-efficient pipeline ADC is presented. Area and power savings are realized by merging the track and hold amplifier (THA) and the 1
^st
-stage multiplying digital-to-analog converter (MDAC), double-sampling the 2
^nd
-stage MDAC and using a 1b sub-range in 4b sub-ADC. It achieves an ENOB of 8.65b with 20.1-MHz input. Including on-chip reference buffers, power and area consumption are 11.2mW and 0.08mm
²
per channel respectively.