32-Mb 2T1R SPRAM with localized bi-directional write driver and ‘1’/‘0’ dual-array equalized reference cell

A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a ‘1’/‘0’ dual-array equalized reference cell for stable read operation.

Introduction

Innovation in computing architecture with normally-off and instantly-on functions for further power reduction is strongly required to realize a sustainable green IT world. To achieve this, large-scale non-volatile RAM, which features both non-volatility and an infinite number of write cycles, is a key device. SPRAM is the most promising candidate. Accordingly, we previously developed a 2-Mb chip [1] having a tunnel magnetoresistive (TMR) device with a synthetic ferrimagnetic (SyF) layer [2]. However, for further large-scale integration, a small memory cell and compact array structure with the necessary writing current and its distribution is necessary, as is stabilized reading operation adaptive to environmental change. Therefore, we have developed the solutions shown in this paper, implemented them in a 32-Mb chip, and demonstrated the chip's successful operation.