Implemenation of simplified architecture of JPEG 2000 MQ Coder

JPEG 2000 is one of the most rewarding image coding standards. A set of practical features are provided which are not available in the previous standards. The features were realized using two new techniques namely the discrete wavelet transform (DWT), and embedded block coding with optimized truncation (EBCOT). The complexity of EBCOT Tier-1 makes its hardware implementations very difficult. In this work, a new simplified architecture for the JPEG2000 MQ-coder is proposed as a primary section of EBCOT Tier-1. The design is for a complete EBCOT Tier-1 process, and it considers system level issues such as the need for buffering. Hardware architecture for the proposed process was developed, realized in VHDL, and synthesized for implementation on FPGA XILINXSL for family Virtex II Pro FG 456.