Comprehensive design methodology of dopant profile to suppress gate-LER-induced threshold voltage variability in 20nm NMOSFETs

We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enables to reduce the threshold voltage (V
_th
) fluctuation in nMOSFETs at high V
_d
by 15%. We have clarified by direct carrier profiling and 3D simulation that the parallel implantation makes lateral extension edge smooth (less roughness induced by gate LER). Thanks to reduced fluctuation in effective channel length, we have made it possible to operate 20-nm nMOSFETs with the V
_th
variability as much as pMOSFETs have.