An I-IP based approach for the monitoring of NBTI effects in SoCs

In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor V
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degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure used to make the SoC/System aware of the NBTI effects. This scheme is conceptually validated by using multi-level simulation and models. The discussion of possible exploitation models completes the paper.