On pinning issues on multicore systems

In recent years, a trend towards multi-core architectures with a growing number of cores for all standard instruction set architectures can be observed. To utilize the full potential of such novel microprocessor architectures, applications running on them must be efficiently parallelized and carefully analyzed regarding runtime, speedup, and parallel efficiency. With multi-core architectures becoming more and more complex, it is essential to compare available hardware with respect to how efficient an application can run on it. Within this context, several x86 based architectures have been tested. Besides the well known SPEC OMP benchmarks, pinning was also tested for a numerical simulation program based on sparse matrix operations. Benchmark tests were carried out on dual quad core Intel Nehalem based systems as well as on AMD Shanghai based systems. In addition, front side bus based systems, namely a dual quad core Intel Clovertown and a quad six core Intel Dunnington were investigated with respect to pinning.