Implementation of plasticity in MOS synapses

Discusses learning, multiplication and other algorithms for a fully-connected artificial neural network in which synaptic weights between neurons are represented by resistances, the output of a neuron producing an analogue voltage V/sub i/ (in the range O to +V/sub 0/ volts) which is a function of a weighted sum of its inputs. The strength or weight W/sub ij/ of the connections is controlled by the channel conductance of a MOSFET with gate voltage V/sub c/ stored on the capacitor. When the synthetic neural circuit produces both +V/sub j/ and -V/sub j/, an inhibitory weight may be realized using -V/sub j/. In this way, all weights W/sub ij/ can be positive. Attention is restricted to excitatory synapses, for specificity; inhibitory synapses may be handled in a similar manner. The weight W/sub ih/ is adjusted according to a learning algorithm and this has normally been performed off-chip and applied as V/sub c/. To increase/decrease the weight it is necessary to alter the charge on the capacitor.<
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