Single-clock dynamic latches optimization

The advantage of using single-phase clocked circuits in VLSI system design is well known. This class of circuits has the advantage of a simple clock distribution, low area for clock routing, reduced clock skew and high speed. However, it is difficult to choose the best configuration of such devices. Indeed, clear estimation criteria are needed to compare various kinds of latches. Moreover, to find the best sizes of the transistors in these latches, an automated procedure is needed. In this paper, a simple compound criterion is proposed. This criterion is used in a proposed automated search procedure. That procedure is then applied to the split-output latch to obtain good configurations. The effect of imposing a stringent balance to the latch characteristics is also described.