A SystemC platform for Network-on-Chip performance/power evaluation and comparison

In modern system-on-chips the communication architecture is a crucial part of the design for performances and power constraints because the number of modules is increasing due to continuous integration scale. Network-on-Chip (NoC) architecture lets to obtain greater performances over the traditional communication architectures. NoC design is more complex because there are more components and networks have more configuration parameters, so designers must explore a wider solutions space in the fastest way possible; fast tools for early stage NoC performance/power analysis are necessary. We propose a SystemC class library and relative tools for comparing NoC and investigating communication bottlenecks. NoC are compared by packet delay statistical analysis and power dissipation is evaluated on NoC components activities; probabilistic investigations, temporal evolutions and a packet tracing tool allow to discover, identify and localize bottleneck.