Temporal coding schemes for energy efficient data transmission in Systems-on-Chip

While device technologies continue to shrink, the careful management of the signal integrity issues in Systems-on-Chip is becoming more important due to its impact to delay and power consumption. A class of two new kind of bus encoding schemes exhibiting temporal redundancy is proposed to cope with the energy and delay problems of long on-chip interconnects. They induce no wiring overhead and at the same time are independent from the bus bit width. These novel techniques achieve both to reduce switching activity and the probability of appearance of many crosstalk patterns and even eliminate them. On-chip interconnects in modern multi-core embedded systems with increasing complexity play a crucial role with regard to wiring overhead and power consumption. Contrary to the perception of limited value of bus encoding for SoCs, due to that they prove beneficial only for very long on-chip wires, designers can take advantage of these novel encodings schemes since, it is common to transfer data on-chip without continuous processing. Thus, data can be maintained in encoded format and hence, the designer does not need to consider the overhead imposed by the conversion to the original un-encoded format when transferring data over each intermediate hop.