A case study of system synthesis with non-synthesizable components using extended VHDL

Extensions to VHDL have been defined in order to produce a compiler that allows for system design with synthesizable and non-synthesizable multi-chip subsystems. The compiler has been completed and this paper presents a case study that has been made to evaluate the merits and limitations of this approach. Finally, a brief discussion is made of the error generation. Capability that results from the use of formal methods in the definition of the VHDL language extensions.