An 800 MHz 1-micron CMOS pipelined 8-bit adder using true single-phase logic-flip-flops

An 8-bit adder, operating at 800 MHz, and a single-stage bit-serial adder, running at more than 1 GHz, have been implemented and successfully tested in a standard 1.0 /spl mu/m CMOS process. The performance was achieved through the use of carry-increment full adders, fine-grain pipelining, and merging the combinational logic into the pipeline registers.