A time/space switch LSI with a 300-Mb/s CMOS low-power I/O interface

This paper introduces a 156 Mb/s/spl times/6 time/space switch LSI for SDH cross-connect systems. To minimize I/O power consumption, we implemented a low-power differential CMOS I/O circuit which can apply to up to 622-Mb/s data transmission. The chip was designed by using a silicon compilation tool and fabricated using 0.5-/spl mu/m CMOS process technology. Functions up to 300-Mb/s I/O operation and 0.9-W total power consumption have been confirmed. This chip uses a 208-pin plastic QFP with a multi layer lead structure.