A chip set for MPEG-2 video encoding

A VLSI architecture for compression and encoding of digital video signals according to the MPEG-2 Video standard is described. The chip set is based on four different ASICs, implemented in HCMOS4 technology. Each of the ICs controls an external memory space which can be realized with conventional DRAM parts. The chip set is controlled by external standard microcontrollers and includes on-chip RISC machines for programmable options. With these ICs, low complexity real-time MPEG-2 encoders can be implemented as well as high complexity/high quality encoders for standard resolution video and HDTV.